The BRM1553 5 Mb/s IP core, transceiver and transformer are ideal for applications where it’s desirable to leverage MIL-STD-1553’s familiar multi-drop bus topology, protocol and hardware-level and API software interfaces, but requiring a higher data rate than 1 Mb/s.
This IP core, transceiver and transformer operate over standard MIL-STD-1553 70 to 85 ohm twisted/shielded cable and provide a 5 Mb/s data rate.
The BRM1553 5 Mb/s IP core is based on Sital’s popular BRM1553D MIL-STD-1553 core. This includes providing the same register and memory hardware/software interface as the BRM1553D and offers several host interface options. These include a local, parallel synchronous interface, PCI, PCI Express and SPI.
If necessary, Sital can provide a “simple system” type interface with no memory and not requiring a host processor. In addition, Sital can also provide additional types of host interfaces and other features that customized and optimized in order to satisfy specific requirements.
For support of the BRM1553-5Mb/s IP core, Sital offers API/library/driver software.
Sital’s MIL-STD-1553 API consists of over 150 low-level and high-level function calls for use in BC, RT, Monitor or RT/Monitor modes.
Sital can provide its API/library with drivers for VxWorks 6.9, 7.0 or 653; Linux 3.0, LynxOS, Pico/Linux or Petalinux; Windows; PikeOS, Green hills Integrity or bare metal (no OS). The software is provided with full documentation and sample programs.
• 5 Mb/s Data Rate using standard MIL-STD-1553B protocol over “1553-like” multi-drop topology with 70 to 85 ohm twisted/shielded cable
• MIL-STD-1553 Intellectual Property Core for FPGAs and ASICs
• Supplied with transceivers and isolation transformers for 5 Mb/s operation
• Provides 1553 BC, RT, MT and RT/MT operating modes
• Architecturally compatible with DDC® Enhanced Mini-Ace® and Micro-Ace® and operates with Sital API/library/driver software
• Parallel Local Bus, 33/66MHz PCI, 1x PCI Express or SPI back-end interface
• Small FPGA area utilization
• Modular architecture allowing flexible implementations
• Provided as vendor and technology independent VHDL netlist code
• Configurations available: Simple Front-End, Local Bus, PC, PCIe and SPI interfaces
Sital’s cutting-edge, innovative “SnS” Technology designed for IP Core’s physical layer.
The patented “SnS” analyze all DataBus messages and provides 2 unique capabilities: