EBR-1553 IP Core
Specified to operate at a higher data rate of 10 Mb/s !
EBR-1553 is a communication standard based on MIL-STD-1553 but is specified to operate at a higher data rate of 10 Mb/s. EBR-1553 operates over a hub (star) topology, with the Bus Controller (BC) node at the center of the hub and RTs located out on the spokes. The EBR-1553 physical layer calls for point-to-point connections using RS-485 transceivers.
High-Speed Data Transmission for Advanced Applications
EBR-1553 is based on MIL-STD-1553’s familiar command/response protocol, thereby enabling deterministic communication and providing error detection. In addition to its 10 Mb/s data rate, the MIL-STD-1553 response time and intermessage gap time values are modified for 10 Mb/s operation. EBR-1553 is deployed on weapon systems, including Small Diameter Bomb (SDB).
Sital’s EBR-1553 IP core provides DDC’s Enhanced Mini-ACE register/memory architecture; BC, RT, and Monitor operation. It also includes a hub that can be instantiated to provide any number of ports up to and including 32.
The core can be supplied with software API/library/drivers for Windows, VxWorks, and Linux. The API/library/drivers provide the same API that Sital provides for its MIL-STD-1553 IP and standard (single-function) boards and is also compatible with DDC’s AceXtreme API.
BC Mode and Hub Operation
For EBR-1553, the BC is the center point of the hub or star topology. The hub can be specified to be able to connect to any number between 1 and 32 RTs, with each hub branch connecting to a single EBR-1553 remote terminal (RT) over an RS-485 physical layer link.
The BC manages the operation of the hub. For non-broadcast messages, the BC selects which of the hub’s connections is active for each individual message. For broadcast messages, the RS-485 transmitters (but not receivers) will be active for all branches of the hub.
The width (number of branches) for the hub is a synthesis parameter that must be provided prior to Sital supplying the EBR-1553 IP core. The BRM1553D-EBR IP core can also support an RS-485 multi-drop configuration.
RT Mode
In RT mode, the IP core is connected to a single RS-485 transceiver, which is connected to one of the ports of the BC.
The RT address can be set by means of hardware pins or by software.
All mode codes are supported, as well as illegalization of mode codes and commands.
Monitor Mode
In Monitor mode, the IP core does not transmit messages; it only receives them. In this case, the hub width parameter is programmed to “1”. The Monitor might also connect to a wider hub, i.e., to multiple hub stubs. However, at any given time, it can only be programmed to record a message transmitted to and received from a single RT at any given time.
RT / Monitor Mode
Similar to Sital’s MIL-STD-1553 IP, components and boards, the BRM1553D-EBR IP core can also operate as a simultaneous RT/Monitor.
Integrated 1553 FPGA Service
For users of Sital Technology’s EBR-1553 IP core, Sital offers its “Integrated 1553” service for integrating its IP cores and software onto Xilinx SoC or MPSoC FPGAs. Sital’s “Integrated 1553” service leverages Xilinx’s Vivado(C) design suite software.
“Integrated 1553” enables reductions in customers’ times by providing “pre-integrated”, turnkey SoC/MPSoC solutions. It allows them to get their on-chip 1553 IP core(s), processor, and software fully up and running from months to approximately 30 minutes.
The “Integrated 1553” involves providing the on-FPGA interfaces between Sital’s IP core(s) and an on-chip processor such as an ARM Cortex. For Xilinx FPGAs, this typically involves the use of an AXI bus for address/data paths and interrupts.
In addition, it includes the integration of Sital’s API/library, operating system and on-chip interconnect bus (e.g., AXI) low-level software drivers. Before supplying a project to customers, Sital performs testing to verify that customers will be able to use Sital’s API and software stack to access and control Sital’s IP cores through its API.
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- EBR-1553 Intellectual Property for FPGAs and ASICs
- Suitable for any EBR-1553 BC, RT, MT implementation
- Compatible with DDC® ACE® and Enhanced MINI-ACE® interface and functionality, works with existing software drivers
- Eliminates risks related to parts obsolescence
- Small FPGA area utilization
- Accommodates various clock frequencies, minimizing clock domains
- Adaptable modular architecture for versatile implementations
- Interface options of 16/32/64 bits
- Allows up to 31 transceivers per BC Hub
- Configurable for Dual-Redundancy setup
- Includes a comprehensive verification environment
- Developed using VHDL code that is independent of vendors and technologies
BC/RT/Monitor Architecture
Includes DDC® Enhanced Mini-ACE® register and memory interface, thereby providing compatible with existing drivers and applications. At the same time, it reduces risk and eliminates the need to re-write existing software drivers and/or applications.
Manchester Decoder
Sital’s unique Manchester decoder can work from a single clock source of any clock frequency of at least 120 Mhz. This reduces the number of clock inputs and clock domains on board, which reduces EMI/RFI and eases the integration with the IP core’s back-end interface.
Advanced algorithms for filtering out noise and disturbances enable the core to operate in harsh EMI environments.
* Mini-ACE® and DDC® are legally registered trademarks owned by Data Device Corporation based in Bohemia, New York, USA. Sital Technology, Ltd. has no affiliation with Data Device Corporation.
