SPI Master IP Core

small circuit board BRD1553SPI-P

For support of its SPI-to-MIL-STD-1553 IP core and SPI-to-MIL-STD-1553 board, Sital offers its SPI Master IP core. The 1553 IP and board products include SPI target interfaces. The SPI Master IP provides a high-performance means for accessing and controlling them.

The major motivation driving Sital to develop this IP core was that commonly available SPI Master controllers don’t provide the level of performance needed for managing a real time SPI slave such as Sital’s BRM1553SPI IP core. There are two factors affecting the performance of a SPI interface. These include the SPI clock rate and the cycle-to-cycle time. While available SPI masters are able to operate well at high clock rates including up to 50 MHz, their cycle-to-cycle delay times can be unacceptably long, sometimes on the order of milliseconds.

Sital’s SPI Master IP core is optimized to allow an on-chip processor on an SoC or MPSoC FPGA to be able to access the core at low-level through on-chip data buses such as AXI for Xilinx. AXI is a high-performance bus, enabling 100 MHz, 32-bit continuous burst transfers.

An important issue that sometimes arises is that many of the real time transactions for accessing the BRM1553SPI IP core consist of blocks of data, such as 32 16-bit words (64 bytes).

In SPI, if 64 bytes are transferred in 64 individual SPI cycles, transferring a single byte with each cycle, then each such cycle requires an address + command which are sometimes 4 bytes, resulting in an inefficiency of at least 5x overhead. Sital’s SPI Master IP is optimized for burst mode support for working with API read and write operations for supporting block mode transfers.

An additional enhancement of Sital’s SPI Master IP is to provide two similar SPI controllers operating through a common external SPI interface that can operate in a “Ping Pong” (double-buffered) approach. The Host CPU may program one of the controllers to write 32 16-bit words, and before this operation is completed, also configure the second controller to read 256 words of 16 bits from the Monitor. Using this configuration, the second controller will begin its read operation immediately after the first controller finishes its write operation. This provides far better performance than can be achieved by host software implementing these two operations sequentially.
The depth of the SPI RAM block is 4096 bytes (2048 16-bit words), enabling the user to send or receive blocks of any length up to 4096 bytes.

• SPI Master Interface IP Core
• High performance Interface
• Includes double-buffering to support “ping-ponged” read and/or write SPI interfaces
• Enables multi-word streaming transfers at serial data rates up to 50 MHz.
• Greatly reduces cycle-to-cycle time delays for streaming transfers
• Optimal for use with SoC or MPSoC FPGAs
• Includes 4096-byte (2048 16-bit words) SPI RAM block enables sending or receiving data blocks of any length up to 4096 bytes.

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  • Description: Single Program Development License for SPI Master IP Core, Including 10 prototype units

  • Description: Single-instantiation IP core hardware key chip for SPI Master IP core

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