Within a client’s system, SitalsBRM1553 MIL-STD-1553 FPGA IP core, designed according to MIL-STD-1553 standards, successfully completed all real-time validation assessments conducted by Test Systems Inc.
While conducting the examination, concerns were raised regarding the system under test’s resistance to noise interference. Noise Rejection Tests are performed during the RT Validation test in section 5.3. It is the last test in 1553 RT Validation, and is done by sending multiple 1553 messages to the RT, polluted by noise of predefined characteristics.
In this case, the system under test used a very marginal 1553 transceiver which suffered from bad symmetry and created a considerable DC offset. This system failed the noise test (although by just a bit – 130mV instead of 140mV).
Needless to say, Sital’s IP core passed the same tests many times in the past, with various transceivers and configurations.
The customer had 2 other similar boards that passed the tests at his own lab (with similar equipment as in Test Systems Inc.), but he decided to use the worst-case board for the RT validation testing.
Nevertheless, Sital took it upon itself to improve the noise immunity of its IP regardless of the quality of the transceiver. The alternative for this customer was to re-spin his board and switch to another transceiver component.
For context, the BRM1553 and EBR1553 MIL-STD-1553 IP cores feature adaptive noise rejection capabilities, designed to ensure reliable communication even in environments with significant electromagnetic interference (EMI).
By dynamically adjusting to noise levels, these IP cores can filter out noise-induced errors, maintaining data integrity without requiring physical changes to the hardware. This capability is crucial in avionics and military applications where communication lines often operate in electromagnetically noisy environments.
Improvements in the IP cores include enhanced symmetry and DC offset correction techniques. These enhancements are vital for mitigating the effects of imperfect transceiver components, which can lead to signal degradation and communication errors.
By compensating for these hardware limitations within the IP core, Sital ensures that data transmission remains robust and reliable, even when using components that are not ideal due to their physical characteristics or cost constraints.
Sital’s ability to quickly modify and improve the IP cores in response to discovered vulnerabilities underscores the flexibility and adaptability of using FPGA-based IP cores for critical communications. This rapid response capability allows for the swift implementation of solutions to emerging challenges, such as increased noise interference, without necessitating hardware redesigns or replacements, thereby saving significant time and resources.
After some modifications to the IP core, the same system passed the noise test with very good results.
“This is a clear example of the advantage of using an IP core,” stated Duli Yariv, Sital’s Vice President for Sales and Marketing. He further remarked, “Within a few days we provided an effective solution, preventing the customer from going through the long and costly process of making changes to his board”.
We, therefore, recommend our customers to update their IP core to the newest version.
This update is free for customers under support.
