SPI Master IP Core

Home > SPI Master IP Core

High efficiency SPI Master IP core optimized for SPI-to-MIL-STD-1553 IP core and board

Sital’s customers have no challenge achieving real-time performance with our super-efficient SPI master!

Why is real-time performance hard to achieve with SPI:

The 1553 SPI node is always an SPI target, and the host CPU is the SPI master. Many customers use the SPI master as supplied by Single Board Computer (SBC) and FPGA vendors.

SPI master can be configured to very high-speed SPI serial clock, up to 50Mhz.

However, the SPI clock is usually not the problem, and speeding it up does not solve real time failures. The problem is caused by one of:

  1. Cycles Throughput – the latency between two consecutive SPI cycles.
  2. Burst Cycles – The in-ability to perform burst SPI block transfers.


Cycles throughput:

We have seen SPI masters that gap 100s of uSec between two SPI cycles. For some reasons those SPI masters have large idle time after each transfer, before they start a new transfer. Trying to optimize the SPI driver is very challenging and requires lots of support from the SBC or FPGA vendor.

Burst Cycles:

SPI supports bursting. MIL-STD-1553 basic data block is 32 x 16 bit words. It is very common to transfer blocks to and from the SPI-to-1553 device. Transferring this block in 32 SPI cycles, where each cycle contains the address and the command is by far slower than transferring an SPI block with a single address and command, followed by 32 x 16 bits.

We would estimate that users that lack both capabilities would not be able to achieve real time operation with an SPI-to-1553 solution !


Sital Technology’s Solution:

For our standard SPI-to-1553 solutions, Sital provides the BRD1553SPI daughter board and the BRM1553SPI IP core with native SPI burst capabilities.

For FPGA’s SPI master, Sital provides an SPI master block that is mapped as memory on internal FPGA bus (AXI bus), and achieves back-to-back SPI transfers, while each transfer supports up to 2048 16-bit words bursts.


More information about Sital’s SPI real-time solution:

The major motivation driving Sital to develop this IP core was that commonly available SPI Master controllers don’t provide the level of performance needed for managing a real time SPI slave such as Sital’s BRM1553SPI IP core. There are two factors affecting the performance of a SPI interface. These include the SPI clock rate and the cycle-to-cycle time. While available SPI masters are able to operate well at high clock rates including up to 50 MHz, their cycle-to-cycle delay times can be unacceptably long, sometimes on the order of milliseconds.

Sital’s SPI Master IP core is optimized to allow an on-chip processor on an SoC or MPSoC FPGA to be able to access the core at low-level through on-chip data buses such as AXI for Xilinx. AXI is a high-performance bus, enabling 100 MHz, 32-bit continuous burst transfers.

An important issue that sometimes arises is that many of the real time transactions for accessing the BRM1553SPI IP core consist of blocks of data, such as 32 16-bit words (64 bytes).

In SPI, if 64 bytes are transferred in 64 individual SPI cycles, transferring a single byte with each cycle, then each such cycle requires an address + command which are sometimes 4 bytes, resulting in an inefficiency of at least 5x overhead. Sital’s SPI Master IP is optimized for burst mode support for working with API read and write operations for supporting block mode transfers.

An additional enhancement of Sital’s SPI Master IP is to provide two similar SPI controllers operating through a common external SPI interface that can operate in a “Ping Pong” (double-buffered) approach. The Host CPU may program one of the controllers to write 32 16-bit words, and before this operation is completed, also configure the second controller to read 256 words of 16 bits from the Monitor. Using this configuration, the second controller will begin its read operation immediately after the first controller finishes its write operation. This provides far better performance than can be achieved by host software implementing these two operations sequentially.
The depth of the SPI RAM block is 4096 bytes (2048 16-bit words), enabling the user to send or receive blocks of any length up to 4096 bytes.

• SPI Master Interface IP Core
• High performance Interface
• Includes double-buffering to support “ping-ponged” read and/or write SPI interfaces
• Enables multi-word streaming transfers at serial data rates up to 50 MHz.
• Greatly reduces cycle-to-cycle time delays for streaming transfers
• Optimal for use with SoC or MPSoC FPGAs
• Includes 4096-byte (2048 16-bit words) SPI RAM block enables sending or receiving data blocks of any length up to 4096 bytes.

Select a Document below to view a PDF:

HSID Manual

Select products for quote:

Supporting SPI-to-MIL-STD-1553 IP core and SPI-to-MIL-STD-1553 board

for Free Evaluation and hardware Samples

safe illustration

Safe and Secure DataBus Solutions

Sital’s cutting-edge, innovative “SnS” Technology is designed for IP Core’s physical layer. Our solutions offer unprecedented cyber security and DataBus fault finder capabilities.


We supply our products with DO-254 and DO-178 certifiability, including DAL A. Our partners: Logicircuit and ConsuNova provide the DO-254 and DO-178 artifacts. Through enhanced physical layer monitoring, the patented “SnS” analyzes all DataBus messages and provides 2 unique capabilities.

2024©All rights reserved