FPGA and ASIC IP Core for MIL-STD-1553B
Sital’s BRM1553D MIL-STD-1553 IP core is a fully compliant BC/RT/Monitor IP building block that has passed 1553B RT Validation testing performed by multiple third parties. This validation testing has included Sital’s own MIL-STD-1553 transceivers and transformers. Sital’s MIL-STD-1553 transceiver features the industry’s lowest power consumption, along with a mechanism to eliminate residual voltage dynamic offset, or “tails”. The BRM1553D IP core can also operate with other suppliers’ transceivers and transformers.
The BRM1553D includes a high-speed synchronous back-end interface between a host processor and the core’s internal registers and dual port RAM. The BRM1553D’s register and memory architecture stores messages, along with control and status information in its shared memory. To enable the re-use of existing software, this memory/register architecture provides hardware-level compatibility with DDC®’s Enhanced Mini-ACE®, Mini-ACE Mark3®, Micro-ACE®, Total-ACE® and Nano-ACE®.
Sital delivers its IP cores in “agnostic” VHDL netlist format, allowing it to be instantiated to any manufacturer’s FPGA family. The IP has been successfully ported to FPGAs from Xilinx, Intel/Altera, Microsemi and Lattice. The core is provided with simulation scripts and test bench code, including a bus tester VHDL model.
As with of Sital’s 1553 IP cores, the BRM1553D core is able to minimize FPGA logic resources by providing synthesis options for RT-only, BC-only, MT-only, RT/MT, BC/MT, and BC/RT/MT versions of the IP.
The cores are available with software APIs/libraries/drivers for Windows, VxWorks and Linux. As require, Sital can also provide drivers for other operating systems. These API/libraries/drivers provide API-level compatibility with DDC’s AceXtreme® library.
The BRM1553D, like all of Sital’s MIL-STD-1553 solutions, is available certifiable to DO-254 up to and including DAL A, with certification artifacts available from Sital’s third-party partner, Logicircuit. Similarly, its 1553 software drivers are available certifiable to DO-178 up to and including DAL A, also with certification artifacts available from Logicircuit.
Another IP and software option that Sital can provide for the BRM1553D and other 1553 solutions is its Safe and Secure (SnS) technology. By means of enhanced continuous physical layer monitoring, Sital’s SnS sensors are able to detect cyber authentication (“spoofing”) violations. The SnS sensors can also detect and locate intermittent and continuous electrical faults in the 1553 bus and stub cables, couplers, connectors, terminators and connected LRUs to help insure platform readiness.
- MIL-STD-1553 A and B Compliant IP for FPGA and ASIC designs
- Supports Bus Controller, Remote Terminal and Monitor multi channel implementations(RTMT)
- DO-254 DAL A compatible
- Compatible with Data Device Corporation (DDC®) Micro-ACE®, Total-ACE®, Mini-ACE®, Enhanced Mini-ACE® and Mini-ACE® Mark3 chipset families and functionality, works with existing software drivers
- Supports any clock frequency, reduces clock domains
- Provided with full verification environment
- Passed full RT validation testing by 3rd party
- Based on vendor and technology independent VHDL code
- Multiple versions available including front end (bare metal), PCI, AXI, SPI and cyber secured versions.
- Includes advanced wiring fault detection capability for improved aircraft maintainability
- Device drivers for : VxWorks 7.0, Linux, Embedded Linux, Integrity, QNX , PikeOS
Select a Document below to view a PDF:
- BRM1553D Product Brief
- MIL-STD-1553 IP Core Type Selection Guide
- BRM1553 IP Core Differences
- White Paper: Mil-Std-1553 IP Cores – A Short Introduction to an Emerging Technology
- Safe and Secure 1553 IP Core Product Brief
- Avionic Databus Cyber Protection
- Sital SnS Description
- Sital DO-254 and DO-178 Certification Process Overview
- BRM1553D Hardware Manual
- BRM1553D Hardware/Software Interface Document (HSID)
- BRM1553 Software API Reference Manual
- BRM1553D Hardware Key License
Select products for quote:
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Description: BC/RT/MT FPGA IP Core, DDC API Interface -
Description: BC/RT/MT FPGA IP Core with Real-Time Cyber Anomaly Detection -
Description: BC/RT/MT FPGA IP Core , Front End