Total Octava vs. Total ACE – A Head-to-Head Comparison

What is Total Octava?

Sital Technology’s and Micross Hi-Rel Components’ Total-OCTAVA MIL-STD-1553 BC/RT/MT terminal has been designed by Sital and is manufactured and tested by Micross. It is designed to be a drop-in replacement for Data Device Corporation’s (DDC®) Total-ACE®. This white paper presents how the Total-OCTAVA is both a drop-in replacement for DDC® and also how it provides specific advantages over the Total-ACE® in a number of areas.

About Sital Technology

Sital Technology offers best-in-class IP cores for MIL-STD-1553 and other data buses, specializing in integrated FPGA solutions. Sital’s IP cores can work with any FPGA and provide accelerated processing. They are highly parallelized, allowing multiple operations to be executed simultaneously. Sital provides smart, robust, and affordable solutions for high-reliability communication buses including MIL-STD-1553, ARINC-429, CAN bus and EBR-1553. With extensive collaboration with industry leaders including Micross, AMD/Xilinx, Lattice, Micross, Logicircuit and Consunova, Sital offers all-inclusive solutions including both hardware and software.

Advantages of Total Octava as a Drop-in Replacement

Sital’s Total-OCTAVA was designed to be a form, fit, function drop-in replacement for Data Device Corporation’s (DDC®) Total-ACE®. It can be populated on boards designed for DDC®’s Total-ACE® without the need for any PC board changes. Further, as Total-OCTAVA provides full compatibility at the hardware register bits and memory data structures level, it can be used without requiring any changes to user driver software or application software.

In addition, if customers are using DDC®’s AceXtreme library and drivers, Sital is able to supply software that’s compatible with DDC® at the API level. This allows customers to re-use application software originally written to operate over DDC®’s API.

As evidence for Total-OCTAVA’s compatibility with DDC®’s Total-ACE®:

1. Since 2011, Sital began supplying its OCTAVA product to Elbit Systems Israel. Sital’s OCTAVA is a drop-in replacement for DDC®’s Enhanced Mini-ACE. Just as DDC®’s Enhanced Mini-ACE was the predecessor to Total-ACE®, Sital’s OCTAVA is the forerunner to Total-OCTAVA.

Sital has delivered over 6,000 OCTAVA components for use on Elbit’s ANVIS (Aviator’s Night Vision Imaging Systems) program. This system is flying on two US Army helicopters and includes two OCTAVAs per LRU.

2. Sital has had zero (0) returns of OCTAVAs from Elbit. The Total-OCTAVA is identical to the OCTAVA, but in a different package and with the addition of two isolation transformers.

Sital’s Total OCTAVA has been supplied to multiple customers. They’ve received recent positive feedback from two of these:

1. The first customer removed their DDC® Total-ACE® from their board and replaced it with Sital’s Total-OCTAVA. This customer then ran its RT and BC software drivers and test application software written for Total-ACE®. The software operated seamlessly with the Total-OCTAVA, producing the same results as with Total-ACE®. This customer did not need to make any changes to its drivers or test code.
2. This first customer then supplied their board with the Total-OCTAVA to their customer. This customer ran their application software through the first customer’s BC and RT software drivers. Once again, the Sital Total-OCTAVA produced the same results as DDC® Total-ACE® running the same application software.

Host Interface

The operation of Total-OCTAVA’s host interface is fully based on that of Total-ACE®. The following paragraphs describe the operation of Total-OCTAVA’s 16-bit buffered non-zero wait mode interface using a 16 MHz clock.

As a means of demonstrating its compatibility with DDC®, Sital exercised its host processor interface timing. For read and write accesses, this demonstration produced the set of waveforms shown in Figure 1.

This demonstration included an emulated host processor operating from a 100 MHz clock instantiated in a Xilinx FPGA. The Total-OCTAVA includes a separate FPGA from the Xilinx FPGA emulating the host. The waveforms shown in Figure 1 were captured from the Xilinx FPGA.

Also, relative to this demonstration, please note:

• Since this demonstration used separate (non-multiplexed) address and data buses, the Total-OCTAVA’s ADDR_LAT input signal was hardwired to logic ‘1’ (transparent latch configuration).
• The input signals STRBD*, SELECT*, MEM/REG* and RD/WR* are developed on the Xilinx FPGA from a 100 MHz clock. Because of that, these signals are asynchronous with the operation of the Total-OCTAVA’s internal state machines and its IOEN* and READYD*output signals.
• Although not a requirement for Total-OCTAVA, for this demonstration, the STRBD* and SELECT* input signals were connected together.
• Figure 1 shows three memory write cycles followed by three memory read cycles.

Some observations relative to this timing diagram:

1. The Total-OCTAVA’s IOEN* output signal asserts low after the first rising edge of CLK when STRBD* and SELECT* are both sampled low. This duplicates the operation of DDC®’s Total-ACE®.
2. For both write and read cycles, the delay from the IOEN* output asserting low to the READYD* output asserting low is a single clock cycle. This compares favorably against DDC®’s Total-ACE®, for which this delay is two clock cycles for write accesses and three clock cycles for read accesses.
3. Following the de-assertion (rising edge) of STRBD* (and also SELECT*), the READYD* and IOEN* outputs go high immediately (asynchronously), rather than staying low until the next rising edge of CLK. This duplicates the operation of DDC®’s Total-ACE®.
4. Please note this diagram does not show any instances of contended accesses. With DDC®’s Total-ACE®, for the case of an internally contended access between the internal protocol logic and a host memory or register access and assuming a 16 MHz clock input, it’s possible for the delay between the STRBD* input asserted low to the IOEN* output asserted low to increase from the maximum time of 117 ns for an uncontended access to as long as 4.6 µS for a contended access.

Since the Total-OCATVA’s shared RAM is a true dual port RAM, it will never encounter a contended access. As a result, the maximum time from STRBD* asserted low to IOEN* asserted low will always be less than two full clock cycles (125 ns with a 16 MHz clock) and the full cycle time from STRBD* low to READYD* low will always be less than three clock cycles (187.5 ns at 16 MHz).

Micross Hi-Rel Components

The Total-OCTAVA is manufactured by Micross Hi-Rel Components at its facility in Apopka, FL. Micross is a leading supplier of high-reliability products and services for military/aerospace, space, medical, industrial and commercial customers. Micross serves these markets with the most comprehensive range of hi-reliability microelectronic components and services available and is the largest hi-rel microelectronics OSAT (outsource semiconductor assembly and test) provider located in the United States. In particular, Micross Hi-Rel Components is a leader in the assembly and testing of standard and custom microelectronic solutions.

Manufacturing

For customers assembling Total-OCTAVAs to their board assemblies, it’s manufactured to withstand reflow temperatures of up to 250°. This includes:

• Micross uses a high-temperature solder inside Total-OCTAVA. Although the precise manufacturer and type is a Micross trade secret, this solder is able to withstand an MCM-to-board assembly reflow solder of 250° C. As a result, the internal solder will not reflow during the next higher assembly (board-level) reflow attach process.
• The non-conductive epoxy used for holding down the isolation transformers is Henkel 84-3. This is a proven material for this application.
• The material for the Total-OCTAVA’s BGA balls is SnPb 63/37. Micross can also accommodate customers requiring RoHS (unleaded) solutions.

Some additional aspects of Micross’ manufacturing materials and processes of Total-OCTAVA include:

• For encapsulating the Total-OCTAVA, Micross uses a hard pot epoxy. Similar to the high-temperature solder, this material is also a Micross trade secret.

Although the selected substrate (PC board) material isn’t characterized for MSL level, it features specs for water absorption of less than 0.5% with a typical value of 0.08%.

While testing will need to be performed, based on its experience, Micross is highly confident that the use of its selected hard pot epoxy encapsulation and substrate material will enable it to satisfy the requirements of MSL-3.

• Component screening for Total-OCTAVA is performed in accordance with MIL-STD-883 and JEDEC standards.

JTAG Interface with Boundary Scan

As a means for performing a quick test of its I/O drivers and receivers and board interconnects, the Total-OCTAVA includes JTAG boundary scan for its digital input and output signals. The Total-OCTAVA’s JTAG port also enables upgrades or bug fixes of fielded Total-OCTAVAs. Note that Sital manages an errata list of length 0. They currently have no known issues with Total-OCTAVA, and if such were to occur, they can be corrected immediately due to the nature of the Total-OCTAVA platform.

ESD and Latch-up

The Total-OCTAVA’s ESD and latch-up performance is characterized as follows:

• ESD-HBM (human body model): Class 2 (200 to < 400V). This compares favorably against DDC®’s Total-ACE®, whose typical ESD sensitivity is characterized as Class 0.
• ESD-CDM (charged device model): Class C1 (250 to <500V)
• Latch-up I-Test Data: Class II (> ±100 mA)
• Latch-up V_Supply Overvoltage Data: Class II (> 1/5x V_CC)

FPGA-based Solution

Rather than including a digital ASIC, the Sital/Micross Total-OCTAVA instantiates all logic and memory in an FPGA. The use of an FPGA provides multiple advantages over ASICs:

• Improved obsolescence mitigation by eliminating the need to spin a new ASIC chip.
• Use of an FPGA enables Sital/Micross to supply customized versions of Total-OCTAVA that are tailored to specific applications.
• If necessary, FPGA code can be easily updated to correct bugs or incompatibilities that materialize, including in fielded units. With ASICs, this isn’t possible.
• The FPGA in Total-OCTAVA is built on a modern 28 nm FD-SOI process, resulting in reduced power consumption and increased integration. This FPGA incorporates all internal logic, 1 Mbit of RAM, and a portion of the transceiver in one component.
• Further, this FPGA fabric is space qualified and will perform better at high altitudes. Its 28 nm FD-SOI process delivers improved reliability by providing a Soft Error Rate (SER) up to 100 times lower than similar FPGAs in its class.

Key Features: Total Octava vs. Total ACE

When comparing the Total-OCTAVA and Total-ACE, both serve as critical solutions for MIL-STD-1553 communication protocols, but they offer distinct features tailored to different needs. Below is a breakdown of their key attributes:

Total-OCTAVA

• Functionality: Total-OCTAVA integrates Bus Controller (BC), Remote Terminal (RT), and Bus Monitor (MT) in one component. It includes flexible memory configurations and optimized performance.
• Memory: Offers 64K x 16 RAM, ensuring low latency and reduced access times, crucial for tight synchronization between BCs and terminals.
• Design: Based on FPGA technology, Total-OCTAVA benefits from improved obsolescence mitigation, flexibility for customized solutions, and the ability to correct bugs or incompatibilities even in fielded units.
• Cyber Resiliency: Incorporates a BC firewall to detect spoofing BCs, as well as wire fault detection for identifying open and short circuit faults on buses and related components.
• Power Efficiency: Features reduced power consumption, with total active dissipation at 100% duty cycle of only 435 mW, much lower than the 1.91 W of the Total-ACE.
• Enhanced Synchronization: The host interface is optimized for reduced access times, guaranteeing tight synchronization for BCs and time tag registers.
• Compliance: Designed to meet DO-254 certifiability standards, with design artifacts available for customers requiring certification.

Total-ACE

• Functionality: Also a Bus Controller, Remote Terminal, and Bus Monitor, Total-ACE provides reliable, high-performance communication for MIL-STD-1553 applications.
• Memory: While offering solid performance, Total-ACE’s memory configuration is slightly less flexible compared to Total-OCTAVA.
• Design: Built on ASIC technology, Total-ACE offers reliability but lacks the customization flexibility of FPGA-based designs, making it less adaptable for specific application needs.
• Cyber Resiliency: Does not have built-in BC firewall capabilities or wire fault detection features.
• Power Consumption: Higher total power dissipation compared to Total-OCTAVA, with active transceiver dissipation at 703 mW under full duty cycle conditions.
• Synchronization: The host interface has higher access times, which may result in increased CPU and bus utilization.

While both solutions provide robust MIL-STD-1553 communication, Total-OCTAVA offers superior flexibility, power efficiency, and cyber resiliency, making it a more modern and adaptable choice for various applications.

Advantages of Total Octava as a Drop-in Replacement

Feature/Spec	Sital/Micross Total-OCTAVA	DDC® Total ACE®	Advantage/Benefit
Functional Compatibility	✓	✓	Pin-for-pin compatible BC/RT/MT Architecture Registers Memory data structures
Maximum total power dissipation: Total MCM, non-transmitting	165 mW	396 mW	Total-OCTAVA: lower power consumption and dissipation
Maximum total power dissipation: Total MCM, 100% duty cycle	435 mW	1.91 W
Maximum active transceiver dissipation at 100% duty cycle	270 mW	703 mW
Real-time transmitter residual voltage (aka dynamic offset or “tails” mitigation)	✓	— (factory trim only)	Realtime adjustment to compensate for changes in power supply voltage, temperature, and component aging
Host Interface: STRBD*-to-READYD* memory/register access time	Two clock cycles	Four clock cycles for reads. Three clock cycles for writes	Total-OCTAVA: reduced access times minimize CPU and host bus utilization. Guarantees extremely tight synchronization for starting multiple BCs simultaneously or resetting or setting multiple terminals’ time tag registers.
Host interface: Worst case contended memory/register access time (assuming 16 MHz clock)	Always < 187.5 ns (no contended accesses)	4.6 µS (worst-case contended access)
BC Firewall	✓	—	Detects spoofing BCs, with option to invalidate spoofing messages
Detecting spoofing BCs or RTs	✓	—	Sital’s Safe and Secure feature detects spoofing BCs or RTs
Wire fault detection	✓	—	Detects, characterizes, and locates open and short circuit faults on buses, couplers, connectors, stubs, and terminations
IRIG-106 Chapter 10 Monitor	✓	—	Provides standardized file format for monitored MIL-STD-1553 messages
Logic implementation	FPGA	ASIC	Total-OCTAVA: improved obsolescence mitigation, capability to supply custom solutions and implement bug fixes, including in fielded units
ESD withstand (Human Body Model)	Class 2	Class 0	Total-OCTAVA: higher ESD withstand voltage
DO-254 Certifiability	✓ — Design artifacts available	✓ — In-use history	Some end customers prefer design artifacts over in-use history

How to Get Free Total Octava Samples

Micross has a worldwide network of direct salespeople, representatives and distributors. If you’re interested in free Total-OCTAVA samples to evaluate, please contact one in your area.