Sital Extends it’s BRM1553 IP with Error Injection Testing Capabilities

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Sital Extends it’s BRM1553 IP with Error Injection Testing Capabilities

Until now, BRM1553 IP cores delivered to customers were mainly targeted for in-flight applications. This means that no errors are allowed to be generated from the system.

However, a recent customer application required Mil-Std-1553 testing capabilities from an already-existing flight system, so that the same system can be used as a bus simulator on the ground or as an in-flight operational system.

Multi-RT feature is an essential feature for a Mil-Std-1553 bus simulator. It means that a single 1553 node can be programmed to act as many 1553 Remote Terminals. The user can program the Remote Terminal (RT) addresses which are simulated and thus the unit will answer and create messages, as requested by a Bus Controller (BC) for the simulated RTs.

The Error Injection feature enables the system to simulate several types of errors which may occur on a 1553 network. Therefore, errors like Parity Error, Sync. Error, Zero-Crossing Error and others are all part of an advanced 1553 test and simulation system.

Same Hardware for Interface Card and Test Benches.

Many avionics vendors, who develop avionic systems, are required to provide test benches for their systems. In many cases, developing the test bench is a high cost project, requiring development of boards, software and other simulation tools, usually at low volumes. Therefore the advantages of developing a single hardware that can be used both as a flight system and as a bus simulation tool are obvious. First – there is only need to develop a single hardware, and not require equipment from additional vendors for bus simulation and testing. Second – customers can re-use the software written originally for the actual system also for testing, ensuring lower development cost and enabling faster time to market.

Of-course, the customer needs to make sure that the test software is not loaded into the operational systems. This can be achieved by having a separate FPGA load file for each system and also by enabling or disabling the Multi-RT and Error Injection features by hardware. This means that the IP core can enable or disable the features, by reading hardware configuration bits, which are set differently between the tester and the in-flight system.

Both features can be added to Sital’s standard BRM1553D, BRM1553PCI and BRM1553FE Mil-Std-1553 IP core and are provided with software API, so that users can easily implement these test features into an existing Mil-Std-1553 system.

Sital Demonstrates Significant Improvement of Noise Durability for BRM1553 and EBR1553 MIL-STD-1553 IP Cores

Close-up of circuit board with green LED indicator

As part of a customer’s system, Sitals BRM1553 MIL-STD-1553 FPGA IP core recently passed all the RT validation tests at Test Systems Inc.

During the test, an issue was raised regarding the noise immunity of the system under test.

Noise Rejection Tests are performed during the RT Validation test in section 5.3. It is the last test in 1553 RT Validation, and is done by sending multiple 1553 messages to the RT, polluted by noise of predefined characteristics.

In this case, the system under test used a very marginal 1553 transceiver which suffered from bad symmetry and created a considerable DC offset. This system failed the noise test (although by just a bit – 130mV instead of 140mV).

Needless to say, Sital’s IP core passed the same tests many times in the past, with various transceivers and configurations.

The customer had 2 other similar boards that passed the tests at his own lab (with similar equipment as in Test Systems Inc.), but he decided to use the worst-case board for the RT validation testing.

Nevertheless, Sital took it upon itself to improve the noise immunity of its IP regardless of the quality of the transceiver. The alternative for this customer was to re-spin his board and switch to another transceiver component.

After some modifications to the IP core, the same system passed the noise test with very good results.

“This is a clear example of the advantage of using an IP core.” Said Duli Yariv, Sital’s VP for Sales and Marketing. “Within a few days we provided an effective solution, preventing the customer from going through the long and costly process of making changes to his board” he added.

We, therefore, recommend our customers to update their IP core to the newest version.

This update is free for customers under support.

Sital Announces the Availability of 10 Mbit MIL-STD-1553 IP Cores

Eight integrated circuits on a circuit board

Sital Technology announced today that it completed the design of the Enhanced Bit Rate (EBR) 1553 Intellectual Property core for FPGA.

EBR-1553 is a 10Mbps bit rate protocol that utilized the robust Mil-Std-1553 protocol over RS-485 transceivers in a hub-based point-to-point connection. Using a star network topology between BC & Remote Terminals enables robust and high-speed data transfer.

Sital’s EBR-1553 IP core’s based on Sital’s proven BRM1553D 1553 IP cores, with DDC® Enhanced Mini-Ace® compatible interface. The ones available are Remote Terminals, Bus Controller as well as Bus Monitor IP Core configurations. The BRM1553D core can work with any FPGA, and requires only a standard RS-485 transceiver, which supports 10Mbps.

Users of Sital’s EBR-1553 IP core can select the core configuration (BC, RT, MT), clock frequency, memory configuration and FPGA family. The back-end interface can be targeted to a local-bus, PCI bus or simple FIFO/registers read/write bus.

The IP Core is provided with software drivers for Windows, Linux, and QNX along with high-level API. The API is fully compatible with DDC API, so that software developers already used to the DDC interface can easily transfer their existing applications to EBR.

An EBR-1553 tester is also available, utilizing the exact same hardware as the commonly used MultiComBox™, only with updated firmware.

“We are very pleased that we can now deliver high-speed EBR-1553 IP to our customers” said Duli Yariv, Sital’s VP Sales and Marketing. “Customers will enjoy the robustness of the 1553 protocol at a high speed of 10Mbps over the very low-cost RS-485 transceivers, with the ability to easily integrate the core into their FPGA and application” he added.

Ofer Hofman, Sital’s CTO pointed that “unlike other vendors’ solutions, Sital’s is a complete solution that includes all modes of operation – BC, RT and Monitor – along with software drivers and EBR tester hardware”.

The EBR-1553 IP core joins the Sital’s growing family of Mil-Std-1553, Arinc429, CAN, WB-194 and other reliable serial bus communication IP cores and solutions.

For more information please contact us at: https://sitaltech.com/products-main-page/ebr-ip-core/

PCI-to-MIL-STD-1553 IP Core

The newly released PCI IP core was developed in order to overcome problems related to existing BRM1553D,BRM1553FE and BRM1553PCI IP cores, specifically in the aerospace industry, where high reliability, wide temperature range and easy integration are key.

Ofer Hofman, CTO of Sital said: “While working on a project with a PCI core from one of the FPGA vendors, we discovered that the core we used doesn’t work in high temperature, even though the temperature was within the range of the component. We concluded that this is due to timing problems created by the core.

Another FPGA vendor provided us with a core that was very hard to integrate. We therefore used our extensive now-how and developed our own core, which is now successfully used in several projects”.

The core can be used for any FPGA and is provided in VHDL source code.

Sital Announces the Release of the OCTAVA MIL-STD-1553 Component

Sital Technology, the leader in Mil-Std-1553 IP cores and products, announced today the release of OCTAVA™, a Mil-Std-1553 communication engine, compatible with DDC® Enhanced MiniACE® devices.

The OCTAVA™ family integrates the BRM1553D Mil-Std-1553 protocol engine, a dual 5-volt transceiver, memory management, processor interface logic and 4K or 64K words of RAM in a 72 pin Plastic Quad Flat Pack (PQFP) package. The family consists of bi-directional data buffers and internal address latches to provide a host processor bus with direct interface. The memory management scheme for RT mode provides three data structures for buffering incoming and outgoing data. Combined with the extensive interrupt capability, these structures serve to guarantee data consistency whilst off-loading the host processor.

The OCTAVA devices can also boot-up as RT with the busy bit set for 1760 applications. The BC mode implements several features aimed at providing an efficient real time software interface to the host processor including flexible interrupt generation, automatic frame repetition, programmable inter-message gap times or message rate, and automatic retries.

The OCTAVA™ devices are pin-to-pin compatible with the DDC® BU-65178 and BU-61688 and as such serve as a perfect drop-in electrical, physical and software replacement. An avionics board designed with the DDC® BU-65178 and BU-61688 can work seamlessly with the OCT-65178 and OCT-61688 without hardware or software changes.

“The OCTAVA™ family completely changes the Mil-Std-1553 market. A market that was previously dominated by a single vendor will now benefit from the power of competition”, said Duli Yariv, VP of marketing for Sital Technology. “OCTAVA™ does not only offer price benefits over the competition, but it also introduces many technology and functional advantages for customers” he added.

OCTAVA™ was introduced in partnership with National Hybrid Inc. (NHi), who designed the transceiver and manufactures the device in the USA.

QuickLogic and Sital Partner to Develop Specialized MIL-STD-1553 FPGA IP Core

QuickLogic and Sital Technology logo

SUNNYVALE, Calif.–(BUSINESS WIRE)–QuickLogic® Corporation (NASDAQ:QUIK – News), the lowest power programmable solutions leader, is expanding its commitment to its military customer base by partnering with Israel-based avionics technology leader Sital Technology to optimize Sital’s MIL-STD-1553 controller design for QuickLogic’s ViaLink® programmable fabric. The MIL-STD-1553 bus is used in military and avionics applications such as heads-up displays, radar, and weapons systems. The controller design will become part of QuickLogic’s Proven System Block (PSB) library for military-grade solutions using the PolarPro® family of programmable platforms.

The MIL-STD-1553 PSB manages all the communications on the bus to and from an attached device. The PSB can act as a bus controller, remote terminal, or monitor terminal interface to the bus, and offers a choice of interfaces on the back end. The PSB is able to provide compatibility with older chipsets that’ve got interfaces targeting legacy controllers, which replaces the legacy device in an existing design without needing any software changes. For new designs a simpler, streamlined interface is available, allowing communications over the bus simply by reading and writing registers.

“Our long-standing military customers are looking for proven MIL-STD-1553 solutions that provide cost-effective flexibility with the long product lifecycles required by their market,” said Mehul Kochar, Business Development Manager at QuickLogic. “We chose to work with Sital for their expertise in these solutions and because their optimized PSB is designed with flexibility in mind.”

“We are excited to be working with QuickLogic to make our technology more available to the US market,” adds Sital Marketing Director Duli Yariv. “Optimizing our design into a PSB for QuickLogic’s programmable fabric will help give a long life to military and civil aerospace designs by removing the risk of parts becoming obsolete as technology changes.” The partnership includes the development of the PSB and will support interface customization for unique designs when needed.

Availability

The MIL-STD-1553 interface PSB will be available for QuickLogic’s PolarPro family of solution platforms in Q3, 2008. PolarPro platforms are already available with full military temperature, shock, and vibration ratings. For more information, go to QuickLogic’s website, www.quicklogic.com.

About Sital Technology

Headquartered in Kfar-Saba, Israel, Sital Technology is an industry expert in MIL-STD-1553 design. The company develops silicon intellectual property for military and avionics applications, provides design services, and offers VHDL training. The principal staff are veterans of the Israeli Air Force with an in-depth understanding of avionics systems and their needs.

About QuickLogic

QuickLogic Corporation (NASDAQ:QUIK – News) is the pioneer and inventor of customizable, innovative semiconductor solutions for mobile as well as portable electronics OEMs & ODMs. These silicon plus software solutions are known as Customer Specific Standard Products (CSSPs). CSSPs allow our customers to have their products brought to market more quickly and remain in the market longer, with the low cost, power and size demanded by the mobile as well as portable electronics market. Visit www.quicklogic.com for more information about CSSPs and QuickLogic.

©2008 QuickLogic Corporation. All rights reserved.

QuickLogic, pASIC, PolarPro, the PolarPro design, QuickPCI, QuickRAM, QuickWorks and ViaLink are registered trademarks, and ArcticLink, the QuickLogic logo & VEE are trademarks of QuickLogic. Other trademarks are their respective company’s property.

Sital Successfully Completes Testing of Wiring Bus Diagnostics IP with an Air Force

Sital Technology has conducted tests of its new patent pending “Tails Code Key” technology for Mil-Std-1553 bus maintenance as part of the BRM1553D IP. The results backed up the theoretical assumptions, previously seen on simulation.

The test was conducted on a F-16 mockup, together with avionics engineers from the Air Force, and proved the need for such technology to overcome wiring and connectors problems, often hard to detect and repair.

“Tail Code Key” is a parametric test that is measured during flight in real time, 50 times a second. These numbers serve as a code – quality code. The code varies as a direct result of the quality of the bus.

If the bus connectors or wires degrade over time and usage, the measured code would change. Technicians get an early warning for problems that should be fixed before they fail the bus.

“I am excited to see theory comes to life”, says Ofer Hofman, founder and R&D Manager of Sital Technology.

Duli Yariv, VP Marketing and Sales of Sital adds: “Tails Code Key will allow Air Forces to dramatically shorten efforts related to avionics bus maintenance. This technology will enable our customers to save time, costs and efforts, currently required, on problems that are related to avionics bus malfunctions and even take preventive measures to fix problems before they occur.”

“Tails Code Key” technology will be integrated with Sital’s successful BRM1553D, BRM1553PCI and BRM1553FE Mil-Std-1553 IP Cores, used by military and aerospace customers around the world.

Sital Announces New IP for Aircarft and Vehicle Data Bus Diagnostics

Close-up of a blue circuit board

“Tail Code Key” is a method of enhancing MIL-STD-1553B and CAN bus maintenance quality by means of performing real time parametric testing on the bus. If functional testing results with “go” and “no-go”, which could be scaled as grade 100 and grade 0, “Tail Code Key” is a parametric test that will deliver a grade somewhere between 0 and 100.

There are three important benefits which are gained from the detailed grade:

The ability to detect failures before they impact functionality.
Physical location of failure on the bus.
Detection of single failure events during flight.

“Tail Code Key” is a set of numbers that are measured during flight in real time, 50 times a second. These numbers serve as a code – quality code. The code varies as a direct result of the quality of the bus.

If the bus connectors or wires degrade over time and usage, the measured code would change. Technicians get an early warning for problems that should be fixed before they fail the bus.

If single failure events occur during flight from physical stress or temperature changes, these single events impact the code, thus escape the tolerated margins. These events are recorded for repair. These single events downgrade the avionics communication quality exactly when they are critically needed. Typically such failures would not be traceable when the mission is complete.

Once the mission is done, bus problems are very hard to debug and require special equipment to pinpoint the exact physical location of the problem. In many cases the location is not found because the test is performed on wheels in 1G and in room temperature. Analyzing a recorded key code unveils the location of the problem.

The Tail Code Key technology is seamlessly integrated with Sital’s BRM1553D, ARINC825 and CAN bus IPs and enables advanced maintenance application development for avionic and automotive applications

If you would like to receive more information, then please contact us.

NASA selects Sital’s BRM1553D IP for MIL-STD-1553 Space Equipment Communication

Kfar Saba, Israel – November 16, 2005 – Sital Technology, a leading provider of military standard Intellectual Property (IP) cores, announced today that NASA, the National Aeronautics and Space Administration, will be using the company’s MIL-STD-1553B IP Core, the BRM1553D, for their deep space mission logic designs.

NASA chose Sital’s product after a rigorous selection process during which it was thoroughly tested against several other competing products. It will be implemented inside a space environment hardened Field Programmable Gate Array (FPGA) which incorporates several electronic circuits to create a general purpose MIL-STD-1553B Remote Terminal.

Featuring the smallest gate count in the industry, Sital’s BRM1553D MIL-STD-1553B IP core offers highly improved reliability over other 1553 solutions. The product connects the back-end user logic with the front-end, a standard MIL-STD-1553B Muxbus which enables real-time management by connecting all the subsystems of avionics and satellite systems.

Sital’s product provides high levels of robustness, flexibility and ease-of-use and, in contrast with most cores and devices, does not require a CPU to manage the backend. It is also one of the few IP cores on the market that passed the RT Validation tests, a set of complex qualification tests required to connect to the front-end and ensure complete reliability.

“Sital’s product answered NASA’s requirements on several levels. They were looking for a product that would enable them to easily connect their data sources and data targets on the back-end, and would not require a CPU for managing the backend,” said Ofer Hofman, founder and R&D Manager of Sital Technology. “NASA’s decision to use an IP core, rather than a discrete device, is a significant milestone in the 20 year history of the MIL-STD-1553B standard. It signals an industry-wide trend towards using the more reliable and easily customizable IP cores for FPGAs instead of the expensive and inflexible single source 1553 IC chips.”

Sital’s IP cores are available for Remote Terminal and Bus Monitor applications. An IP core for Bus Controller applications will be available in Q1 2006. Sital’s business model enables the company to customize pricing models per the customer’s specific needs.

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