Sital Technology announced today that it completed the design of the Enhanced Bit Rate (EBR) 1553 Intellectual Property core for FPGA.
EBR-1553 is a 10Mbps bit rate protocol that utilized the robust Mil-Std-1553 protocol over RS-485 transceivers in a hub-based point-to-point connection. Using a star network topology between BC & Remote Terminals enables robust and high-speed data transfer.
Sital’s EBR-1553 IP core’s based on Sital’s proven BRM1553D 1553 IP cores, with DDC® Enhanced Mini-Ace® compatible interface. The ones available are Remote Terminals, Bus Controller as well as Bus Monitor IP Core configurations. The BRM1553D core can work with any FPGA, and requires only a standard RS-485 transceiver, which supports 10Mbps.
Users of Sital’s EBR-1553 IP core can select the core configuration (BC, RT, MT), clock frequency, memory configuration and FPGA family. The back-end interface can be targeted to a local-bus, PCI bus or simple FIFO/registers read/write bus.
The IP Core is provided with software drivers for Windows, Linux, and QNX along with high-level API. The API is fully compatible with DDC API, so that software developers already used to the DDC interface can easily transfer their existing applications to EBR.
An EBR-1553 tester is also available, utilizing the exact same hardware as the commonly used MultiComBox™, only with updated firmware.
“We are very pleased that we can now deliver high-speed EBR-1553 IP to our customers” said Duli Yariv, Sital’s VP Sales and Marketing. “Customers will enjoy the robustness of the 1553 protocol at a high speed of 10Mbps over the very low-cost RS-485 transceivers, with the ability to easily integrate the core into their FPGA and application” he added.
Ofer Hofman, Sital’s CTO pointed that “unlike other vendors’ solutions, Sital’s is a complete solution that includes all modes of operation – BC, RT and Monitor – along with software drivers and EBR tester hardware”.
For more information please contact us at: https://sitaltech.com/products-main-page/ebr-ip-core/