H009 and I6PP194 IP Cores

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IP Cores for F-15 and F-16 Designs in FPGAs and ASICs'

Sital’s IPH9194D IP core provides complete protocol, memory management and host interface logic for the General Dynamics 16PP194 (WMUX) and McDonnell-Douglas H009 data bus protocol standards. This includes protocol logic for 16PP194 CIU (Control Interface Unit) and RIU (Remote Interface Unit) modes, along with H009 CCC (Central Computer Complex) and RU (remote unit) modes. The core also includes the protocol logic for monitoring of both 16PP194 and H009 buses.


The IPH9194D core’s registers and memory organization provide compatibility with DDC’s Enhanced DDC Mini-Ace, Micro-Ace and Total-ACE, thereby enabling reuse of existing software drivers. The IPH9194D core includes a high-speed synchronous back-end interface between a host processor and the core’s internal registers and dual port RAM. The IPH9194D’s register and memory architecture stores messages, along with control and status information in its shared memory.

Sital can provide versions of its MIL-STD-1553 transceivers and isolation transformers that provide compliance with both the 1553 and WMUX standards. Many applications requiring 16PP194 (WMUX) also require MIL-STD-1553. In these cases, it’s common for the 1553 BC (bus controller) and the WMUX CIU to operate over the same physical data bus.

Most 16PP194 (WMUX) applications also require MIL-STD-1553. In these cases, it’s common for the 1553 BC (bus controller) and the WMUX CIU to operate over the same physical data bus. For such applications, Sital can supply both its BRM1553D and IPH9194D cores for applications that require 1553 and WMUX to co-exist on the same data bus. In these applications, both protocols’ controllers — the 1553 BC and the WMUX CIU – operate most efficiently from the same node, rather than from separate nodes for each of the two protocols.

Such a fully integrated and autonomous solution provides significant advantages for performing 1553 BC (Bus Controller) and WMUX CIU (Control Interface Unit) message scheduling. This includes the capability to control and access messages and control data for both protocols through the same software API.

This single-node implementation enables scheduling of all 1553 and WMUX messages along the same timeline, thereby preventing message collisions. This allows for message retries for failed 1553 or WMUX messages and also enables the insertion of asynchronous messages without the risk of collisions from 1553 and WMUX messages sent simultaneously on the same bus. Such an architecture offloads and reduces complexity for host software for both the 1553 BC and the WMUX CIU.


Sital delivers its IP cores in “agnostic” VHDL netlist format, allowing them to be instantiated to any manufacturer’s FPGA family. Sital’s IP cores have been successfully ported to FPGAs from Xilinx, Intel/Altera, Microsemi and Lattice. All Sital cores are provided with simulation scripts and test bench code, including a bus tester VHDL model.

As with all of Sital’s 1553 IP cores, the BRM1553D core is able to minimize FPGA logic resources by providing synthesis options for 16PP194 CIU-only, RIU-only, Monitor-only, RIU/Monitor, CIU/Monitor, and CIU/RIU/ Monitor versions of the IP. Similarly, the core provides synthesis options for H009 CCC-only, RU-only, Monitor-only, RU/Monitor, CCC/Monitor, and CCC/RU/ Monitor.

The IPH9194D core is available with software APIs/libraries/drivers for Windows, VxWorks and Linux. As required, Sital can also provide drivers for other operating systems. All drivers provide API-level compatibility with DDC’s AceXtreme MIL-STD-1553 software.

The IPH9194D, like all of Sital’s MIL-STD-1553 solutions, is available certifiable to DO-254 up to and including DAL A, with certification artifacts available from a third-party. Similarly, its 1553 software drivers are available certifiable to DO-178 up to and including DAL A, also with certification artifacts available from a third party.

Another option that Sital offers for its IPH9194D and other data bus solutions is its Safe and Secure (SnS) technology. By means of enhanced continuous physical layer monitoring, Sital’s SnS sensors are able to detect cyber authentication (“spoofing”) violations. The SnS sensors can also detect and locate intermittent and continuous electrical faults in the 1553 bus and stub cables, couplers, connectors, terminators and connected LRUs to help insure platform readiness.

  • H009 or PP194 Intellectual Property for FPGAs and ASIC
  • Can be integrated with Sital’s MIL-STD-1553 IP cores, so a single IP may be used for all interfaces
  • Backend Compatible to Enhanced DDC, Mini-Ace, Micro-Ace and Total-ACE interface and functionality, and works with existing software drivers.
  • Local Bus or 32-bit, 33/66MHz PCI back-end interface
  • Small FPGA area utilization
  • Modular architecture allowing flexible implementations
  • Provided with full verification environment
  • Based on vendor and technology independent VHDL code
  • Various interface configurations available, including local Bus, PCI interface and SPI

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H009 and I6PP194 IP Cores Brochure

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safe illustration

Safe and Secure DataBus Solutions

Sital’s cutting-edge, innovative “SnS” Technology is designed for IP Core’s physical layer. Our solutions offer unprecedented cyber security and DataBus fault finder capabilities.


We supply our products with DO-254 and DO-178 certifiability, including DAL A. Our partners: Logicircuit and ConsuNova provide the DO-254 and DO-178 artifacts. Through enhanced physical layer monitoring, the patented “SnS” analyzes all DataBus messages and provides 2 unique capabilities.

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