CAN , CAN-FD , ARINC 825 IP Cores for FPGA and ASIC designs. Including real-time detection of cyber anomalies and circuit failures for enhanced reliability and cyber resilience
Sital’s ARINC-429 IP core is fully compliant to the ARINC-429 standard. Sital can supply its ARINC-429 IP cores with up to 16 transmit channel and 16 receive channels, with data rate programmable for all channels (12.5 or 100 Kbps). By means of a proprietary technique, Sital can reduce the logic resource requirements by up to 70% for multi-channel ARINC-429 implementations.
Sital’s ARINC-429 architecture includes 32-bit wide, programmable-depth FIFOs with separate FIFOs for transmitting and receiving. Sital’s 429 decoders include a noise filtering mechanism to enhance receiver robustness. Sital’s 429 receive channel architecture also includes programmable address recognition, with 256 labels for each receive channel; and selection of either even, odd or no parity. Sital’s ARINC-429 IP is supplied as a single VHDL netlist of one or multiple transmit and/or receive channels, and includes a full verification environment.
In addition, Sital can supply ARINC-429 IP with DO-254 certifiability up to and including DAL A, along with VxWorks, Linux and Windows software drivers providing DO-178 certifiability up to and including DAL A. For the certifiable ARINC-429 IP and software, artifacts are available from a third-party company, Logicircuits.
Another capability that Sital can provide for ARINC-429 is its Safe and Secure (SnS) technology. By means of enhanced physical layer modeling, Sital’s SnS can detect cyber authentication violations. In addition, the SnS sensors can also detect and locate electrical faults such as intermittent or continuous open or short circuits in cables, connectors or LRUs.
Features
VHDL netlist delivery. Suitable for all FPGAs and ASIC implementations.
Compliant with BOSCH CAN protocol. DO-254 DAL A certifiable.
Implements CAN version 2.0B with programmable bit rate up to 1Mbit/sec.
ISO 11898-5 compliant.
Physical CAN layer compliant with ARINC 825 for CAN Aviation
Licensed VHDL IP for implementation of a safe and secure CAN controller in FPGA or ASIC .
CPU Interface (PCI/local bus/SPI)
Standard, Extended and Remote frames supported.
8 maskable identifier filters. Filtering on ID and first two data bytes for both
Standard and Extended Identifiers.
Loopback mode for self-test.
Monitor (Listen-only)
32-message Transmit and Receive internal fabric FIFOs.
Internal 16-bit free running counter for time tagging of transmitted or received
messages.
Permanent dominant timeout protection.
Re-transmission disable capability.
Transmit Enable pin.
Supports any COTS CAN transceiver.
Cyber Resilience:
White-listing message IDs.
Monitor all CAN communication from a single instance on the bus.