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For simulation of supplied files Please do the following:

1. Look into the VISUAL directory and learn the test bench structure.
2. Invoke ModelSim VHDL simulation.
3. Change working directory in Modelsim to this root directory.
4. In Modelsim "Tools => execute macro => modelsim.tcl"

This macro will compile and run 1553 simulation, which includes the test bench and the core in VHDL.


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For synthesis of your FPGA with the core:

If you want to integrate the core in your design, please instantiate the
core in your TOP VHDL code the same way it is instantiated in the test bench.

The supplied IP files are vendor independent VHDL gate level, and should be synthesized like your 
other VHDL files, i.e., synthesis them and place and route normally.

Gate level simulation is recommended. You may edit the test bench file to simulate your FPGA
with 1553 transactions.

Good luck.

If you have any question, please do not hesitate to contact Sital technology.

Technical manager - Ofer Hofman:
Cell phone +972 52 2614373  (Israel time zone = +2h)
email : ofer@sitaltech.com
SkyPe : oferhofman
