16PP194 and H009 are multi-drop data buses, and are both predecessors to MIL-STD-1553. Sital Technology offers an IP core and board and tester products providing these two protocols.
16PP194. The 16PP194 standard, aka Weapons Mux or WMUX, was developed by General Dynamics in the mid-1970s. It is used alongside MIL-STD-1553 on F-16 stores (weapons) buses.
16PP194’s physical layer calls for a cable characteristic impedance of 64 to 84 ohms at 1 MHz, with 75Ω ±5% termination resistors at each end of the bus. Similar to MIL-STD-1553, 16PP194 allows for both direct and transformer coupled terminals. 16PP194’s transmitter voltage is specified as 7.3 to 9.9 volts peak-to-peak with 15 loads; with rise and fall times less than 150 ns, and ringing and overshoot <0.5 volts peak-to-peak.
16PP194 receivers must respond to signals with voltages between 1.2 and 10.0-volts peak-to-peak (line-to-line), and must not respond to signal levels below 0.9 volts peak-to-peak. In addition, receivers are required to operate with common mode voltages of up to ±25 volts peak from 0 to 2 MHz, and not be damaged by common mode signals up to ±50 volts peak. Input impedance is required to be ≥1300 ohms at 1 MHz looking into the isolation transformer.
The 16PP194 standard calls for two types of terminals, a CIU (Control Interface Unit) and one or more RIUs (Remote Interface Units). The topology of the 16PP194 standard consists of two separate unidirectional (simplex) data buses, one for message transmissions from the CIU (Control Interface Unit) to the RIUs, and the second one for transmissions from RIUs to the CIU. 16PP194 also calls for redundancy, with a backup data bus.
Similar to MIL-STD-1553, 16PP194 operates at 1 Mb/s and uses Manchester encoding, with the encoding polarity reversed from MIL-STD-1553’s. In addition, the standard calls for a 26-bit word format, with data, status and GO/NOGO words; and 4 μS gaps between words. The 26-bit word includes a sync bit, 4-bit RIU address and subaddress fields, a 16-bit data field and a parity bit with odd parity.
H009. The H009 standard was developed by McDonnell Douglas in the late 1960s for use on F-15 avionics systems. It involves two-way transmission over a pair of data buses between a CCC (Central Computer Complex) and one or more remote units referred to as peripherals. The standard involves synchronous transmission, with a differential 1 MHz clock signal provided by the CCC, along with dual redundancy of the clock and data buses.
H009 operates over 68 ohm twisted/shielded cable, with bus terminations. The clock is specified as a sinusoidal waveform with transformer isolation. For the H009 data signals, the spec also calls for transformer coupling, along with Manchester encoding and requirements for limiting the harmonic content above 1 MHz. The transmitted voltage is required to be 20 ±4V peak-to-peak line-to-line.
An additional requirement for H009 transmitters is for the impedance reflected to the bus to be 68 ohms ±10%. At the end of a transmission, transmitters are required to continue presenting a low impedance (68 ohms) for 3 μS, and then switch to receive mode.
When operating in receive mode, CCCs and peripherals must present a resistive, balanced impedance with a minimum of 10,000 ohms line-to-line to the bus. The receiver voltage range for H009 is ±4 to ±40 volts-peak-to-peak line-to-line. In between words, there is no signal on the bus for 3 μS.
The CCC begins each H009 message by transmitting a 17-bit Select word. The Select word includes a 4-bit address; a command indicator designating either a data or command type message; a 6-bit control field, akin to 1553’s subaddress field; a T/R* (transmit/receive) bit; a 4-bit word count and parity bit. H009 data words include 16 data bits and a parity bit. Further, a Select word must be preceded by 8 μS of “no data” (dead) time.
Peripherals must respond exactly 5 μS after the last bit of the Select word. If the CCC does not see a response from a peripheral within 8 μS following the end of its transmission, it will determine the occurrence of a “No-data” condition from the addressed peripheral. Peripherals distinguish between Select and Data words based on the length of the preceding time gap. This gap is ≥ 8 μS before Select words and 5 μS before Data words. For all transmissions, the receiving CCC or peripheral must verify correct bit counts, word count, parity and time gaps between words.
Sital 16PP194 and H009 Products. As shown in the table below, Sital Technology offers an IP core, transceivers and boards for support of the 16PP194 and H009 protocols. For the IP core, there are accompanying VxWorks and Linux drivers. For the boards, there are accompanying Windows drivers.
The IP and boards provide compatibility at both the register/memory hardware level and also the software API level with both Sital’s MIL-STD-1553 API/library/driver and DDC’s 1553 components and AceXtreme API.
Sital’s MIL-STD-1553 packaged transceiver and transceiver design IP can be used with its 16PP194 IP. Further, Sital can also supply a modified version of its 1553 packaged transceiver and transceiver design IP that meets the requirements of the H009 standard.
MIL-STD-1553 BC and 16PP194 CIU Implementation. Most 16PP194 (WMUX) applications also require MIL-STD-1553. In these cases, it’s common for the 1553 BC (bus controller) and the WMUX CIU to operate over the same physical data bus. Sital is able to provide IP, component or board-level solutions for applications that require 1553 and WMUX to co-exist on the same data bus. In these applications, both protocols’ controllers -- the 1553 BC and the WMUX CIU – operate most efficiently from the same node, rather than from separate nodes for each of the two protocols.
Such a fully integrated and autonomous solution provides significant advantages for performing 1553 BC (Bus Controller) and WMUX CIU (Control Interface Unit) message scheduling. This includes the capability to control and access messages and control data for both protocols through the same software API.
This single-node implementation enables scheduling of all 1553 and WMUX messages along the same timeline, thereby preventing message collisions. This allows for message retries for failed 1553 or WMUX messages and also enables the insertion of asynchronous messages without the risk of collisions from 1553 and WMUX messages sent simultaneously on the same bus. Such an architecture offloads and reduces complexity for host software for both the 1553 BC and the WMUX CIU.
