MIL-STD-1553B BC/RT/MT Protocol engine device
The OCTAVA™ family integrate Mil-Std-1553 protocol engine, a dual 5-volt transceiver, memory management, processor interface logic and 4K or 64K words of RAM in a 72 pin Plastic Quad Flat Pack (PQFP) package.
The family contains internal address latches and bi-directional data buffers to provide a direct interface to a host processor bus. The memory management scheme for RT mode provides three data structures for buffering incoming and outgoing data. Combined with the extensive interrupt capability, these structures serve to ensure data consistency while off-loading the host processor.
The devices can optionally boot-up as RT with the busy bit set for 1760 applications. The BC mode implements several features aimed at providing an efficient real time software interface to the host processor including automatic retries, programmable inter-message gap times or message rate, automatic frame repetition and flexible interrupt generation.
The OCTAVA™ devices are pin-to-pin replacement devices for the DDC® BU-65178 and BU-61688. These replacements offer a software and electrical compatible solution. A board designed with the DDC® BU-65178 and BU-61688 can work seamlessly with the OCT-65178 and OCT-61688 without hardware or software changes.
OCTAVA™ is introduced in partnership with National Hybrid Inc. (NHi), who designed the transceiver and manufactures the device in USA.also includes 2 transformers, eliminating any need for any additional 1553 components.Using BRD1553XVR makes the IP Core evaluation and 1553 applications simple and easy.
P-Orchestra™ channels are software compatible to DDC® Enhanced MiniACE® components and architecture, with 8K word of internal RAM for Module 0 and 16K word of internal RAM for Module 1.
P-Orchestra™ is provided with software drivers for Windows, Linux and QNX, along with high-level API, which ease application development.
Sital’s Luthier™ program for 1553 bus simulation and analysis is also provided. This software includes an advanced GUI (Graphical User Interface) for controlling the board, generating 1553 traffic, monitoring and emulating a real bus environment.
- Fully integrated Mil-Std-1553 noitce 2 compliant terminal
- Second source for DDC® MiniACE®
- Flexible processor/memory interface
- 4K x16, 8K x16, 64K x 16 shared RAM
- 5V only option
- Simultaneous RT/MT mode
- Bootable RT option required for Mil-Std-1760
- Automatic BC retries
- Programmable illegalization
- Operates from 12, 16 or 20 MHz
- 72 pins PQFP 1.3 square inch package
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Description: DDC 1553 MiniAce pin-to-pin replacement component