EBR 1553 FPGA IP Core
EBR-1553 is a 10Mbps bit rate protocol which utilized the robust Mil-Std-1553 protocol over RS-485 transceivers in a hub-based point-to-point connection. Using network topology of a star between BC and Remote Terminals enables high-speed and robust data transfer.
Sital’s EBR-1553 IP core is based on Sital’s proven 1553 IP cores, with DDC® Enhanced Mini-Ace® compatible interface.
Bus Controller, Remote Terminals and Bus Monitor IP Core configurations are available. The core can work with any FPGA, and requires only standard RS-485 transceiver, which supports 10Mbps.
BC Mode and its HUB
In EBR1553 the BC manages a HUB for star topology. This HUB is built of up to 31 RS485 transceivers, each having a single Tx and Rx lines. The decoder and encoders inside the EBR1553D Core were upgraded to handle this single line bus, and assume that the transceivers are biased to ‘1’. This means that when no one transmits on the bus, the Rx line would read ‘1’. Modern RS485 transceivers are internally biased, thus the biasing resistors can be avoided.
The width of the HUB is a synthesis parameter that needs to be provided prior to the supply of the IP core.
The BRM1553D-EBR IP core supports also a RS485 multi-drop configuration.
In RT mode, the IP core is connected to a single RS485 transceiver, which is connected to one of the ports of the BC.
The RT address can be set by software or by hardware pins.
All mode codes are supported, as well as illegalization of mode codes and commands.
In MT mode, there is no transmission, only bus monitoring. In this case the HUB Width is set to 1. The MT might also connect to a wider HUB, i.e. to multiple HUB stubs, but it can only record a single RT response (as EBR1553 defined).
RT / MON Mode
The BRM1553D EBR can function as an RT/MON as in regular 1553. This is a SW optional mode.
- Support of up to 100 Meter long wires!!
- EBR-1553 Intellectual Property for FPGAs and ASIC
- Suitable for any EBR-1553 BC, RT, MT implementation
- Compatible to DDC® ACE® and Enhanced MINI-ACE® interface and functionality, works with existing software drivers
- Eliminates risks related to parts obsolescence
- Small FPGA area utilization
- Supports any clock frequency, reduces clock domains
- Modular architecture allowing flexible implementations
- 16/32/64 bits interface
- Up to 31 transceivers per BC Hub
- Supports Dual-Redundancy configuration
- Provided with full verification environment
- Based on vendor and technology independent VHDL code
- Software drivers and API libraries for Windows, Linux,VxWorks and QNX
Back End Interface
Includes DDC® Enhanced MINI-ACE® interface, compatible with existing drivers and applications.
No need to rewrite drivers’ code
Eliminates replacement risk
The unique Manchester decoder can work with any clock frequency from 120Mhz and up to reduce clock sources and clock domains on board (reduces EMI/RFI) and ease the integration with back-end interface.
Advanced algorithms for filtering out noise and disturbances enable the core to operate in harsh environments.
* DDC® and MINI-ACE® are registered trademarks of Data Device Corporation, Bohemia, NY, USA. There is not any affiliation between Data Device Corporation and Sital technology, Ltd.
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- Enhanced Bit Rate IP Brochure
- 4 Reasons to select FPGA over ASIC design
- EBR1553 Case Study
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Description: Extended Bit Rate MIL-STD-1553 A/B compliant with bus controller, remote terminal and monitor support, with DDC API SW interface compliance