EBR 1553 FPGA IP Core
- Support of up to 100 Meter long wires!!
- EBR-1553 Intellectual Property for FPGAs and ASIC
- Suitable for any EBR-1553 BC, RT, MT implementation
- Compatible to DDC® ACE® and Enhanced MINI-ACE® interface and functionality, works with existing software drivers
- Eliminates risks related to parts obsolescence
- Small FPGA area utilization
- Supports any clock frequency, reduces clock domains
- Modular architecture allowing flexible implementations
- 16/32/64 bits interface
- Up to 31 transceivers per BC Hub
- Supports Dual-Redundancy configuration
- Provided with full verification environment
- Based on vendor and technology independent VHDL code
- Software drivers and API libraries for Windows, Linux,VxWorks and QNX
Back End Interface
Includes DDC® Enhanced MINI-ACE® interface, compatible with existing drivers and applications.
No need to rewrite drivers’ code
Eliminates replacement risk
The unique Manchester decoder can work with any clock frequency from 120Mhz and up to reduce clock sources and clock domains on board (reduces EMI/RFI) and ease the integration with back-end interface.
Advanced algorithms for filtering out noise and disturbances enable the core to operate in harsh environments.
* DDC® and MINI-ACE® are registered trademarks of Data Device Corporation, Bohemia, NY, USA. There is not any affiliation between Data Device Corporation and Sital technology, Ltd.
Select documents and proceed to check out.
Documents will automatically arrive at your email inbox
- Enhanced Bit Rate IP Brochure
- 4 Reasons to select FPGA over ASIC design
- EBR1553 Case Study
Select products for quote and proceed to check out.
Description: Extended Bit Rate MIL-STD-1553 A/B compliant with bus controller, remote terminal and monitor support, with DDC API SW interface compliance