H009/PP194 IP Core for FPGA

H009 and PP194 IP Core for FPGA and ASIC Devices

Combining the benefits of programmable devices (FPGA) and Sital’s IP Cores provides a small-size, robust, reliable, flexible, future-proof and cost-effective solution for Mil-Std-1553, H009 or PP194 interface. Sital’s IP cores are designed for any requirement and application. Customers can choose between various configurations and interfaces. From the very small and simple Front-End (FE), designed for simple applications, where no CPU is controlling the system, to the most complex implementations, where a Local Bus is used by the CPU (D) or where PCI bus is used (PCI). The IP19194D cores are software compatible to DDC® Mini-Ace® and Micro-Ace® Mil-Std-1553 components, thus customers can re-use existing 1553 architectures and know-how for H009 and PP194 applications. All IP Cores work with any FPGA, clock frequency and the Sital Discrete transceiver, providing the most robust, yet flexible, solution.

Feature Summary:
H009 or PP194 Intellectual Property for FPGAs and ASIC
Can be integrated with Sital’s Mil-Std-1553 IP cores, so a single IP for all interfaces
Backend Compatible to Enhanced DDC® Mini-Ace® and Micro-Ace® interface and functionality, works with existing software drivers
Local Bus or 33/66MHz PCI back-end interface
Small FPGA area utilization
Modular architecture allowing flexible implementations
Provided with full verification environment
Based on vendor and technology independent VHDL code
Various configurations available: Local Bus and PCI interface

H009_IP_Block_Diagram

 

Back End Interface
Includes DDC® Enhanced MINI-ACE® interface, compatible with existing drivers and applications.

No need to rewrite drivers’ code
Eliminates replacement risk

 

Specifications

Compatibility
H009/MacAir
PP194 (Wmux)
1Mbps Data Rate
Sinus (H009) or Trapezoid signal when used with Sital Transceiver
Enhanced DDC® Micro-ACE® interface

PCI Interface
PCI specification 2.3 compliant
33MHz performance (66MHz optional)
32 bit datapath
Zero wait states burst mode
Full Target functionality

RAM
4, 8, 16, 32, 64K by 16 bits Dual Port RAM (Limited by FPGA resources only)

Clock
Any even frequency from 12MHz and higher (12, 14, 16… 98, 100MHz, …)
Including 33MHz for PCI and 125MHz for PCI Express implementations

Supported FPGAs
Any FPGA with sufficient number of LUTs and Dual-Port memory
FPGA families from the following vendors: Xilinx, Altera, Lattice, Actel
* For other FPGAs or ASIC please consult Sital

Deliverables
VHDL net list for FPGA vendor and memory
User’s manual
Sample VHDL code that incorporates the core
Synthesis script for sample code

* DDC® and MINI-ACE® are registered trademarks of Data Device Corporation, Bohemia, NY, USA. There is not any affiliation between Data Device Corporation and Sital technology, Ltd.

 

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